Recruitment for Engineer, Staff Design for Test

 

Discretionary Job Title : Engineer, Staff Design for Test
Employee Category : Fulltime-Regular
State : Maharashtra
City : Pune

Qualifications : Emerging and Embedded Business Unit (EEBU) is assembling a highly talented ASIC design team in India to execute next generation state-of-art wireless communication projects.  We are currently soliciting resumes from top notch DFT Engineer with:

• B.Tech or M.Tech in Electrical Engineering with minimum of 8 -10 years of strong, hands on DFT experience

• Must have prior full-chip DFT leadership experience handling large complex ASIC/SoC and should have handled at least one SoC tapeout.

• Should have hands-on experience in DFT tasks such as ATPG, MBIST and repair, LBIST, JTAG (IEEE 1149.1), on-chip scan compression, fault models and fault simulations, ATPG coverage improvements (aiming > 99% coverage) and simulation with timing, at-speed testing, transition and path delay ATPG, Formal verification pre and post DFT insertion, gate level simulations etc

• Excellent debugging skills – scan failures/blockage, DFT DRC failures, timing (setup/hold) failures, signature analysis

• Expertise in industry standard EDA tools for test such as DFT Advisor, fastscan/TestKompress, TetraMax, DFT compiler

• Scripting skills in Perl, Tcl, Xml, Verilog

• Excellent analytical and communication skills

• Experience in working with sites located in different parts of the world.

• Hard working and dedicated

Description :

• Successful candidate will be a Test Lead handling all DFT tasks of large wireless SoCs. He will be the main DFT reference for the design team in India.

• Work closely with design and backend team and define/improve DFT methodology for SoCs

• Will be responsible for full-chip SCAN, ATPG, Boundary Scan, MBIST, LBIST

• Lead full-chip timing closure for all test modes using Primetime

• Signoff on DRC and other DFT verification checks

• Silicon bringup and post silicon debug/diagnosis with close cooperation with Design and Yield.

• Should have working knowledge on manufacturing test systems

• Must be able to gracefully handle aggressive but realistic tapeout plans and crunch time situations Marvell is one of the most innovative companies in the semiconductor industry with an outstanding history of delivering state-of-art